Take advantage of I3C for faster, simpler, and more flexible IC-to-IC communication
A comparison of the system configurations is shown in Figure 2. The four-wire SPI interface can operate faster and supports full duplex communication. I²C communicates using half duplex over a two-wire bus consisting of a clock (SCL) and data (SDA) lines. Both require extra lines to support interrupts and other control functions such as chip select. I3C reduces the number of wires used in the interface to two, eliminating the separate interrupt, enable, and chip select lines used in I²C and SPI. This reduction in wire count is a significant advantage in a system requiring ten to twenty individual
Designers need a more forward- looking interface approach that eliminates these extra conductors from the interconnects and handles those operations in-band using only the clock and data lines. Additionally, the bus should be able to operate at higher speeds and with lower power losses. I3C interface I3C was developed by the Mobile Industry Processor Interface (MIPI) Alliance to address these requirements. The interface is available both as MIPI I3C to MIPI members, and as MIPI I3C Basic with reduced functionality to non-members. Like the legacy I²C
and SPI interfaces, the improved form is serial and is implemented using two wires to minimize pin counts and the number of signal paths between components. It has a data rate up to 12.5 Mbits/s with a 12.5 megahertz (MHz) clock using single data rate (SDR) mode. It operates at lower power levels and uses a simple yet flexible design architecture. Notably, the I3C standard retains limited backward compatibility with the I²C system, allowing existing I²C devices to be connected to the I3C bus, while still allowing the bus to switch to higher data rates for communication between compliant I3C devices.
Figure 2: Comparing the basic configurations of I3C, I²C, and SPI interfaces shows I3C’s improved speed and simpler wiring. (Image source: NXP Semiconductors)
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