sensors tied to the processor, each with several secondary wires. Interrupts and other control lines are replaced by IBIs. In this method, a target sensor or device imposes its address into the I3C bus address header to notify the processor of an interrupt. The difference in clock rates between I²C and I3C is significant. I²C is generally clocked at 100 kilohertz (kHz), 400 kHz, or 1 MHz, while I3C can be clocked at 12.5 MHz. Previously, SPI was used for clock rates higher than 1 MHz. The
design selection was between the clock rate and the number of wires. I3C has changed that by offering higher clock and data rates using a true two-wire topology. Push-pull outputs, which can switch faster than open- drain or collector drivers, are significant contributors to I3C’s increased clock rate. To maintain compatibility with I²C devices, I3C can switch between open- drain and push-pull drivers depending on the bus state. The open-drain or collector design
is used during initial addressing or arbitration, where both I²C and I3C devices may be on the line simultaneously. I3C uses push-pull when communication is unidirectional, and there is no chance of an I²C device communicating simultaneously. In addition to the standard SDR, I3C supports several optional high data rate (HDR) modes. These HDR modes operate with the same clock rate but transmit with a higher data density. The first of the HDR modes is HDR double data rate (HDR-DDR), where data is clocked on both edges of the clock signal, providing nearly two times the data rate. For a 12.5 MHz clock, the DDR mode achieves an effective data rate of 20 Mbits/s. HDR ternary symbols have dual versions: HDR ternary symbol, pure (HDR-TSP) for I3C devices only, and HDR ternary symbol, legacy (HDR- TSL) for buses including both I²C and I3C devices. Ternary symbol modes achieve three data bits per clock using three-bit (ternary) symbols encoded on the SCL and SDA lines. HDR bulk transport (HDR-BT) mode offers the highest data by supporting communications over quad, dual, or single SDA data lines. This results in eight, four, or two times the raw single data rate performance at the same clock rate.
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