The co-processor architecture: an embedded system architecture for rapid prototyping
■ How do the accomplishments of the milestone enable further parallel execution paths?
Built upon the lesson learned from the MCU’s implementation, the designer carries this confidence forward into this next milestone. Tools, such as the aforementioned Vivado HLS from Xilinx, provide a functional translation from the executable C/C++ code to synthesizable HDL. Now, timing constraints, process parameters, and other user preferences must still be defined and implemented, however, the core functionality is persevered and translated to the FPGA fabric. For this milestone, the MCU’s role is that of a system manager. Status and control registers within the FPGA are monitored, updated, and reported on by the MCU. Furthermore, the MCU manages the user interface (UI). This UI could take the form of the web server accessed over an Ethernet or Wi-Fi connection, or it could be an industrial touchscreen interface giving access to users at the point
The digital signal processing with the microcontroller milestone The first development stage that this hardware architecture allows places the MCU front and center. All things being equal, MCU and executable software development is less resource and time-consuming than FPGA and hardware descriptive language (HDL) development. Thus, by initiating product development with the MCU as the primary processor, algorithms can be implemented, tested, and validated more rapidly. This allows algorithmic and logical bugs to be discovered early in the design process, and this also allows for substantial portions of the signal chain to be tested and validated. The FPGA’s role in this initial milestone is to serve as a high- speed data gathering interface. Its task is to reliably pipe data from the high-speed ADC, alert the MCU that data is available, and present this data on the MCU’s external memory interface. Although this role does not include implementing HDL-based DSP processes or other algorithms, it is nonetheless highly critical. The FPGA development performed at this phase lays the foundation for the product’s ultimate success both
Figure 4: Application program, host processor, and FPGA-based hardware - used in satellite communications example.
of use. The key takeaway from the MCU’s new, more refined role is this: by being relieved from the computationally intensive processing tasks, both the MCU and FPGA are now being leveraged in tasks for which they are well suited.
the product’s processes
2. Having been first developed and validated within the MCU, algorithmic risks have been mitigated, and these mitigations are translated over into synthesizable HDL. Tools, such as Vivado HLS, make this translation an easier process. Furthermore, FPGA-specific risks can be mitigated through integrated simulation tools, such as the Vivado design suite 3. Stakeholders are not exposed to significant risk by moving the processes over to the FPGA. On the contrary, they get to see and enjoy the benefits that the FPGA’s speed and parallelism provide. Measurable performance improvements are observed and focus can now be given to readying this design for manufacturing
Figure 2: Architecture – digital signal processing with the microcontroller. Image source: CEPD
within the product development efforts and upon release to the market. By focusing on just the low-level interface, adequate time can be dedicated to testing these essential operations. Only once the FPGA is reliably and confidently performing this interfacing role, can this milestone be concluded confidently. Key deliverables from this initial milestone include the following benefits:
3. The lessons learned
from implementing the algorithms in C/C++ will be directly transferable to HDL implementations – through the use of software-to-HDL tools, e.g., Xilinx HLS The system management with the microcontroller milestone The second development stage, which this co-processor approach offers, is defined by the moving of DSP processes and algorithm implementations from the MCU to the FPGA. The FPGA is still responsible for the high-speed ADC interface, however, by assuming these other roles, the speed and parallelism offered by the FPGA are fully utilized. Additionally, unlike the MCU, multiple instances of the DSP processes and algorithm channels can be implemented and run simultaneously.
Key deliverables form this milestone and include these benefits:
1. Fast, parallel execution of
DSP processes and algorithm implementations are being provided by the FPGA.The MCU provides a responsive and streamlined UI and manages
1. The full signal path – all
amplifications, attenuations, and conversions – will have been tested and validated
2. The project development time and effort will have been reduced by initially
implementing the algorithms in software (C/C++); this is of considerable value to management and other stakeholders, who must see the feasibility of this project before approving future design phases
Figure 3: Architecture – system management with the microcontroller. Image source: CEPD
we get technical
12
13
Powered by FlippingBook