Quickly create low-jitter, high-frequency clocks using a translation loop module
board is not provided in the EV- ADF4401ASD2Z kit. Figure 6 maps out the physical connections of the EV- ADF4401ASD2Z system. The associated Analysis | Control | Evaluation (ACE) Software controls the TL SiP functions. Power is derived from an externally applied 6-volt power supply. The suggested equipment to use with this evaluation board includes a Windows PC, a spectrum analyzer or a signal source analyzer, and three signal generators. The block diagram of the EV- ADF4401ASD2Z shows the ADF4401A module, along with Analog Devices’ HMC3716 PFD, LT6200 op-amp, and the ADG1219 SPDT switch (Figure 7). It is vital to use a PFD that can operate at high frequencies as this minimizes the need for dividers, which can degrade the in-band noise response. The 1.3 GHz phase comparison frequency capability of Analog Devices’ HMC3716 makes it ideal for use in the IF range of the ADF4401A. The ability of such a circuit to compare both frequency and phase eliminates the need for additional circuitry to steer the frequency to the intended output frequency. The HMC3716 becomes the external PFD to complete the offset loop. The high-frequency operation range and ultra-low phase noise floor of the HMC3716 make it possible to design wide- bandwidth loop filters.
Figure 6: An EV-ADF4401ASD2Z setup diagram shows the equipment and connections required to evaluate the ADF4401A, including the SDP-S control board, PC, power supply, signal generators, and spectrum analyzer. Image source: Analog Devices
in translation loop designs. This programmable solution allows engineers to achieve optimized performance on the first effort and reduce time to market. Evaluating the ADF4401A The ADF4401A is designed to help engineers reduce the time to market of high-performance instrumentation, using a frequency generation solution with an RF bandwidth of 62.5 MHz to 8 GHz. By using a down-converting mixer, the ADF4401A has very low in- band noise with a wideband jitter of ~9 femtoseconds (fs) integrated from 100 Hz to 100 MHz. The design and layout techniques inside the ADF4401A enable a typical spurious-free dynamic range of 90 dBc. A package size of 18 x 18 x 2.018 millimeters (mm) substantially reduces board space
compared to a traditional discrete design. To evaluate the device’s performance, designers can use the EV-ADF4401ASD2Z evaluation board (Figure 4). The board includes a complete translation loop, including an external PFD (HMC3716), an active filter (LT6200), and a multiplexer (ADG1609). The EV-ADF4401ASD2Z includes the ADF4401A TL SiP with integrated VCO, a loop filter (5 MHz), a PFD, a USB interface, and voltage regulators. Additionally, the EV-ADF4401ASD2Z requires the EVAL-SDP-CS1Z (SDP-S) system demonstration platform (SDP) (serial) controller board (Figure 5). The board provides a USB connection from a PC to the EV-ADF4401ASD2Z so it can be programmed. The controller
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