Figure 7: The EV-ADF4401ASD2Z evaluation board block diagram shows the key components supporting the AD4401A translation loop. Image source: Analog Devices
phase noise floor of the fixture is approximately -160 dBc/Hz. These together give an rms jitter of 12.53 fs in total.
Conclusion
High-speed instrumentation systems require extremely low-jitter clocks to ensure that the output data remains uncompromised. The challenge for engineers is to find suitable devices that can build the high-speed gigahertz clock system. The ADF4401A translation loop greatly simplifies device selection to build the clock system, providing a compact module that ensures low jitter at higher frequencies, while also reducing board space, cost, and time to market.
In Figure 7, the LT6200 op-amp with an LPF configuration attenuates high-frequency spurs, while the ADG1219 switch completes the system’s translation loop. The EV-ADF4401ASD2Z evaluation fixture creates in-band noise plots and jitter measurements as shown in Figure 8.
input is an SMA100B RF and microwave signal generator. The evaluation board’s LO2 in-band noise is approximately -135 dBc/ Hz which is apparent at low offsets up to 300 kHz. The LO2, ADF4401A module, HMC3716 PFD, and loop filter contribute to an in-band noise of about -140 dBc/Hz. The internal phase noise appears between 5 MHz and 50 MHz, and the
In Figure 8, the LO2 and HMC3716
Figure 8: Single sideband phase noise at 5 GHz output, with an external HMC3716 reference of 500 MHz and external LO at 4.5 GHz. Image source: Analog Devices
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