Use an agile RF transceiver in an adaptive SDR communication system for aerospace and defense
locked loop (PLL) paths: one for the high-frequency RF path and another for the digital clocks and converter sampling clocks. Finally, the device’s digital signal processing block includes an Arm M4 embedded processor that handles self-calibration and control functions (Figure 3). Able to operate in either zero-IF mode or low-IF mode for phase- noise-sensitive applications, the ADRV9002 features transmitter and receiver subsystems offering complete signal chains. Each transmitter subsystem provides a pair of digital-to-analog converters (DAC), filters, and mixers that recombine I and Q signals and modulates them onto the carrier frequency for transmission. Each receiver subsystem integrates a resistive input network for gain control that feeds a current mode passive mixer. In turn, a transimpedance amplifier converts the mixer’s current output to a voltage level that is digitized by an ADC with a high dynamic range. During available transmitter slots in TDD operation or in FDD applications where only one receiver system is used, unused receiver inputs can be used to monitor transmitter channels for LO leakage and QEC, or unused receiver inputs can be used to monitor power amplifier (PA) output signal levels. The latter capability comes into play in the ADRV9002’s integrated
Figure 2: Zero-IF radio architectures can meet the need for higher performance and lower SWaP, but signal isolation is challenging . Image source: Analog Devices
implemented on a single chip (Figure 2). Despite its apparent advantages, the direct conversion architecture presents its own implementation challenges that have limited its widespread adoption. In this architecture, the signal is converted to a radio frequency (RF) carrier at the local oscillator (LO) frequency, but direct current (DC) offset errors and LO leakage can result in errors being propagated through the signal chain. Furthermore, differences in signal paths, even within the same chip, can introduce a gain or phase mismatch of the in- phase (I) and quadrature (Q) signal, resulting in a quadrature error that can compromise signal isolation. SDR technology offers the potential to overcome the limitations of traditional radio architectures, but few solutions can address the broader requirements associated with ADEF applications. Using the Analog Devices’ ADRV9002 RF transceiver, developers can easily meet the need for greater
performance and functionality with the lower SWaP demanded in these applications.
Integrated functionality delivers optimized performance with reduced SWaP Supporting a frequency range from 30 megahertz (MHz) to 6,000 MHz, the ADRV9002 is a highly-integrated transceiver that contains all the RF, mixed signal, and digital functionality required to support a broad array of application requirements. Capable of both time division duplex (TDD) and frequency division duplex (FDD) operation, the device features separate dual-channel direct conversion receiver and transmitter subsystems that include programmable digital filters, DC offset correction, and quadrature error correction (QEC).
Within its on-chip synthesizer subsystem, the ADRV9002 features two distinct phase-
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