second pair can substitute when power consumption is critical. For applications characterized by periodic stretches of inactivity, the ADRV9002’s RX monitor mode can be employed. In this mode, the ADRV9002 alternates between a minimal power sleep state and a detect state at a programmed duty cycle. In the detect state, the device activates a receiver and attempts to acquire a signal over a bandwidth and RX LO frequency programmed by the developer. If the device measures signal power level above the programmed threshold, the device exits monitor mode, and the ADRV9002’s blocks are powered up to handle the desired signal. Rapid prototyping and development To help engineers move quickly into evaluation, prototyping, and development, Analog Devices provides extensive hardware and software support of ADRV9002- based systems. ■ For hardware support, Analog Devices offers a pair of ADRV9002-based cards: ■ ADRV9002NP/W1/PCBZ for low band applications operating in the 30 MHz to 3 gigahertz (GHz) range ■ ADRV9002NP/W2/PCBZ for high band applications in the 3 to 6 GHz range Equipped with FMC connectors, these cards support the onboard ADRV9002 with power regulation
Figure 3: The ADRV9002 RF transceiver integrates dual receive (RX) and transmit (TX) subsystems. Image source: Analog Devices
digital pre-distortion (DPD) feature, which uses its monitored PA signal levels to apply the appropriate pre- distortion required to linearize the output. This capability enables the ADRV9002 to drive the PA closer to saturation, optimizing its efficiency.
designed specifically to help developers find a suitable balance between performance and power. At the block level, developers can deploy power scaling on individual signal path blocks to trade reduced performance for lower power consumption. In addition, the blocks in TDD receive (RX) and transmit (TX) frames can be disabled to sacrifice RX/TX or TX/ RX turnaround times for lower power consumption. To further aid the developers’ ability to optimize power versus performance, each ADRV9002 receiver subsystems include two pairs of ADCs. One pair comprises high-performance sigma-delta ADCs, while the
Tuning power and performance
The ADRV9002 device provides a fully integrated solution in a 196- ball chip scale package (CSP) ball grid array (BGA), as well as minimizing size and weight for SDR ADEF communications systems. To help developers further optimize power consumption, the ADRV9002 integrates multiple features
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