We get technical
RF Design and Components I Volume 14
Virtual antennas simplify IoT embedded antenna design Quickly create low- jitter, high-frequency clocks using a translation loop module How to select and apply antennas for IoT devices Learn the fundamentals of software-defined radio
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4 Virtual antennas simplify IoT embedded antenna design 8 Quickly create low-jitter, high- frequency clocks using a translation loop module
How to implement SWaP-C satcom antenna arrays using SMD power dividers and directional couplers
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20 Use an agile RF transceiver in an adaptive SDR communication system for aerospace and defense 26 Why a good LNA is key to a viable antenna front-end 30 Special feature: retroelectro Wildman Whitehouse and the twenty-five-hundred-mile-long capacitor 48 How to quickly leverage Bluetooth AoA and AoD for indoor logistics tracking 54 How to select and apply antennas for IoT devices 60 Learn the fundamentals of software-defined radio
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Editor’s note Radio Frequency (RF) technology lies at the heart of modern communication, enabling the wireless systems that connect our devices, homes, and industries. From high-speed 5G networks and satellite communications to IoT devices and automotive radar systems, RF systems power the invisible networks shaping our world. For engineers, understanding RF design and its challenges is essential to pushing the boundaries of what’s possible in electronics. RF design is a unique and complex field, demanding a blend of theoretical knowledge, practical expertise, and creative problem-solving. Unlike digital systems, where signals are binary and predictable, RF operates in a dynamic analog domain, where even minor adjustments can have significant effects on performance. Engineers working with RF systems must consider factors like signal integrity, power management, and noise reduction while navigating real-world constraints such as size, cost, and regulatory compliance. The growing demand for wireless technologies has raised the stakes for RF design, pushing engineers to innovate at unprecedented speeds. Whether it’s ensuring the reliability of critical communications in aerospace systems or optimizing power efficiency for battery-operated IoT devices, RF design challenges are more diverse than ever. This diversity calls for a deep understanding of not just the theory but also the components, tools, and techniques that drive successful designs. At DigiKey, we recogni z e the unique challenges engineers face in the RF domain. Designing high-performance systems requires access to the right components, tools, and resources, as well as a strong grasp of the principles that govern RF behavior. By bringing together innovative products and expert support, we aim to help engineers overcome these challenges and develop solutions that meet the demands of today’s connected world. This e-book is designed to inspire and support engineers tackling RF design projects. It is not just a guide to understanding RF technology but a resource for addressing the practical complexities of modern RF systems.
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Virtual antennas simplify IoT embedded antenna design
Antennas have always existed in a contradictory and sometimes confusing place in the wireless world. On one side, they are just simple passive transducers between the confined energy in conductors as represented by voltage and current, and the dispersed, radiating electromagnetic energy existing in a vacuum or air. On the other side, they are available in a bewildering range of physical embodiments, configurations, styles, and sizes. Since the earliest days of wireless
researchers and engineers knew that antenna performance was ultimately governed by Maxwell’s four crisp equations, making use of these equations for antenna design was not possible due to the enormous complexities involved in modeling and computation.
(think Marconi and over a century ago), the conception, design, and fabrication of antennas has gone through several major phases. The first phase The first antennas were based on one of two fundamental structures: the monopole with an associated ground plane (sometimes called a whip antenna) (Figure 1), and the balanced, ungrounded dipole in various configurations such as the folded dipole (Figure 2). While
As a result, antenna-related
Written by Bill Schweber
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analysis was limited to basic equations which were used to size the elements of antennas such as the monopole, dipole, long wire, and a few other configurations. These equations were also modified using rules of thumb, intuition, and field trials. For example, it was known that using tubing rather than thin wires for dipoles increased their bandwidth, which might be good or bad depending on the application; the amount of this increase versus tubing diameter was estimated using guidelines based on experience and basic measurements. Even academic discussions of antenna designs and their operating principles had few equations beyond basic arrangement versus wavelength discussions, as made clear in the 1926 technical paper for the classic Yagi-Uda antenna (Reference 1) (Figure 3).
the availability of models and algorithms that captured antenna attributes, which could be executed on computers to solve the electromagnetic field models and equations in a reasonable amount of time, as long as the models were not too complicated.
These “field solvers” allowed designers of new antenna configurations to use the
combination of antenna theory and field-experience insight to propose new arrangements, model them, and finally quantify their performance “on paper”, without need for a physical model and field tests in their initial design stages. This approach worked to some extent, but it was still somewhat of a hit-or-miss arrangement. It did, however, enable engineers to focus on an antenna design and iteratively adjust and tweak it until it met the project objectives. An extraordinary example of this was seen in the development of the first stealth aircraft, the F-117 Nighthawk, at Lockheed’s
legendary Skunk Works (References 2 and 3). Much the of theoretical work on reducing its radar signature by many orders of magnitude was based on analytical solutions and complex equations. These equations analyzed the reflection of electromagnetic energy fields on the aircraft as it was bathed in radar signals. The project’s objective was to use unique and unconventional choices in skin-panel material, shape, size, angles, joints, and other design elements to minimize the inherent tendency of these surfaces to act as an antenna. This, in turn, caused the aircraft to re-radiate and reflect energy in an antenna-like mode, and thus be invisible to the radar system receiver. Figure 2: The basic dipole is a balanced, symmetrical antenna without a ground reference (top), as shown in the illustration (bottom). Image sources: TCARES.net (top) and Tutorials Point (bottom)
The second phase The second wave of antenna- design innovation began with
Figure 1: The long wire or whip antenna arrangement is a single-element design using a ground plane (here, the car’s surface) (left); the illustration of the antenna shows its simplicity (right). Image sources: Lihong Electronic (left); Electronics Notes (right)
Third phase is very different
We are now entering a new wave of
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Virtual antennas simplify IoT embedded antenna design
functional multiband wireless connectivity, enabling a single antenna booster component to function effectively across multiple mobile and wireless designs, thus reducing time to market, product development investments, and of course, cost. In addition, as the antenna boosters are physically built as chip antennas, they can be installed using conventional pick-and-place systems, resulting in lower production cost and improved quality and reliability. Making a match The matching network is key to realizing the unique booster performance. While the antenna booster is standard and can be used across a variety of mobile products, the matching network does need customization for every product, but this is a one-time, up- front design effort. By changing the matching network, the booster’s RF response can be customized to cover the multiple frequency bands required in a modern IoT device or smartphone. The simpler single-band IoT device needs a matching network with typically three to five
Figure 3: The basic Yagi antenna (top) is a three- element antenna widely used in commercial, residential, and military applications. The three elements (bottom) are a driven (active) dipole element with a passive reflector behind it and a passive director in front of it, all mounted on a single boom. Image sources: EuroCaster/ Denmark (top); RFWireless-World (bottom)
board. The designer tunes it to the desired frequency band(s) by creating and adjusting the matching network’s component arrangement and values. In other words, this arrangement creates a new and beneficial synergy between the antenna booster and the surrounding ground plane. A rough analogy would be the effect of attaching a small audio-piezo driver to a rigid tabletop: the tabletop would resonate and, in effect, significantly boost the resultant audio output level. The Ignion antenna boosters are standard, off-the-shelf, surface- mount components that replace conventional customized planar inverted-F antennas (PIFAs) and printed-circuit antennas. They are much smaller than the operating wavelength, typically below 1/30 or even 1/50 of the wavelength and beyond. They provide fully
model-based antenna design, one which looks at the challenge from a different perspective. Instead of relying on a dedicated antenna to radiate an RF signal, the Internet of Things (IoT) device or smartphone radiates the signal directly from the ground plane. To do this, a conventional embedded antenna is replaced with an Ignion NN03-320 DUO mXTEND antenna booster (Figure 3), a 7.0 millimeter (mm) long × 3.0 mm wide × 2.0 mm high passive component that is roughly one-tenth the size of a traditional antenna (note that Ignion was known as Fractus Antennas until 2021). With its unique and patented Virtual Antenna technology – the commercial name for the “antenna- less” technology based on a new generation of tiny components – this booster is always the same component regardless of the size or form factor of the printed circuit
Figure 4: The Ignion NN03-320 DUO mXTEND is a tiny passive component that uses a product’s circuit board ground plane to radiate the RF signal. Image source: Ignion
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Frequency Regions
Figure 5: The NN03-320 antenna booster can be used for different and/or multiple bands when fitted with the suitable passive component matching circuit between the RF source and the booster. Image source: Ignion the ground plane as a radiating surface. These passive, surface- mount booster devices offer an alternative to conventional embedded antenna arrangements for IoT devices and smartphones. A single Virtual Antenna device can serve different parts of the RF spectrum, simply by appropriate configuration of its passive matching network.
Class
Frequency Range
More detailed info
1561MHz, 1575MHz, 1598MHz to 1606MHz, and 2400MHz to 2500MHz
2 Ports
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GNSS + BLUETOOTH
1561MHz, 1575MHz, 1598MHz to 1606MHz
1 Port
3
GNSS
1 Port
1
2400MHz to 2500MHz
BLUETOOTH
1 Port
1
3400MHz to 3800MHz
5G
3100MHz to 4800MHz and 6000MHz to 10600MHz
1 Port
1
UWB
components, while a multiband smartphone might need a couple of boosters and five to eight high-Q components for its matching network. Ignion simplifies the design effort with a free development tool which lets the designer virtually place the booster near the edge of the circuit board, define a “clear” zone around the booster devoid of components, and then calculate the needed passive comments for the matching network. For the multiport NN03-320, the calculated matching networks allow the device to cover multiple bands and applications including GNSS, Bluetooth, 5G and UWB, over frequencies spanning 1561 to 1606 megahertz (MHz), 2400 to 2500 MHz, 3400 to 3800 MHz, 3100 to 4800 MHz, and 6 to 10.6 gigahertz (GHz) (Figure 5). The NN03-320 datasheet specifies the performance of this 50 ohm (Ω) Virtual Antenna booster component and optimized matching network using standard antenna parameters for each band, including efficiency,
peak gain, VSWR, polarization, and radiation pattern. Application notes show typical matching network schematic diagrams like Figure 6, and include a table of suggested passive component values for each desired frequency span. While these values serve as starting points, they will need to be tweaked to account for unanticipated parasitics, as well as the effects of nearby components such as displays or ICs. Conclusion Antenna boosters such as these from Ignion represent a different way of radiating RF energy by using
Recommended Reading
1. Yagi, Hidetsu; Uda, Shintaro, Proceedings of the Imperial Academy (February 1926). “Projector of the Sharpest Beam of Electric Waves” (PDF). 2. Air Force Magazine, “How the Skunk Works Fielded Stealth ”
3. Ben Rich, “Skunk Works: A
Personal Memoir of My Years of Lockheed ”
Figure 6: This suggested schematic diagram for a dual-band matching network also comes with a table of suggested passive component values to provide a starting point for design, analysis, and evaluation. Image source: Ignion
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Quickly create low-jitter, high-frequency clocks using a translation loop module
Written by Bonnie Baker
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F RF
F
PFD
PFD
Figure 1: The standard PLL locks to a lower frequency (F PFD ) reference and generates an output frequency (F RF ). Image source: Bonnie Baker
VCO
÷N
Designers of instrumentation and measurement systems require low- jitter, spurious-free signals in order to provide the signal-to-noise ratios (SNRs) or error vector magnitudes (EVMs) required to meet increasingly demanding customer requirements. At the same time, they are also facing significant pressure to reduce board footprint as well as design cost, and complexity. The latter is critical in to shortening development time to meet narrowing time-to-market windows. To address the many application challenges, engineers need to transition their instrumentation and measurement clocking solutions from custom-made traditionally discrete designs to more integrated solutions. An important step toward this is to use an integrated translational phase-locked loop (PLL). This allows the frequency up- conversion of a traditional voltage- controlled oscillator (VCO) signal, while substantially maintaining the jitter and phase noise of a fixed external local oscillator (LO).
translation loops towards achieving the industry lowest integrated phase noise. By way of example, it introduces the ADF4401A translation loop system-in-package (TL SiP) from Analog Devices and shows how it addresses performance requirements through an output signal with sub-10 femtosecond (fs) rms wideband integrated jitter capability and enhanced isolation to attenuate spurious components, while also meeting designers’ integration, cost, complexity, and time-to- market needs. Traditional PLL vs. translation loop operations The primary purpose of a translation loop is to generate an output signal locked to an input reference signal with significantly reduced in-band phase noise compared to traditional PLLs. A standard PLL consists of a feedback system containing a phase-frequency detector (PFD), charge pump, low-pass filter (LPF), VCO, and a feedback frequency
This article discusses the role of
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Quickly create low-jitter, high-frequency clocks using a translation loop module
divider N (Figure 1).
F RF
F
The PFD compares the phase of input reference and the phase of the feedback signal and generates a series of pulses proportional to the phase error between them. The charge pump receives the PFD pulses and converts them into current source or sink pulses that will in turn tune the VCO either up or down in frequency. The LPF removes all the pulses’ high- frequency energy and converts them into a voltage that the VCO can use. The VCO’s output signal is fed back to the PFD block through the N divider to complete the loop.
PFD
PFD
VCO
Mixer
Figure 3: A translation loop uses a mixer to down- convert the VCO frequency to the PFD frequency instead of using a traditional feedback divider. Image source: Bonnie Baker
LO
be integer or fractional)
8,000 MHz = N × 160 MHz N = 50
F PFD is the PFD frequency Figure 1’s in-band noise floor is calculated using Equation 2: In - band noise floor = FOM PLL + 10 log 10 (F PFD ) + 20 log 10 (N) Where FOM PLL is the PLL’s in-band phase noise floor figure of merit (FOM) Consider an example with an in- band phase noise floor FOM of -234 decibels per Hertz (dB/Hz); a PFD frequency (FPFD) of 160 megahertz (MHz), and an output frequency (FRF) of 8 gigahertz (GHz). For this system, Equation 1 is used to calculate the value of N: F RF = N × F PFD
Equation 2 is used to calculate the in-band noise floor: In-band noise floor = FOM PLL + 10 log 10 (F PFD ) + 20 log 10 (N) = -234 dBc/Hz + 10 log 10 (160e6 Hz)
Figure 1’s frequency transfer function is calculated using Equation 1: F RF = X x F PFD
Where F RF is the output frequency N is the feedback divider ratio (can
+ 20 log 10 (50) = -118 dBc/Hz
In the calculation above, the N divider strongly contributes to the overall in-band noise floor, with 20 log 10 (50), equaling 34 dB. A smaller N value would decrease the in-band noise floor; however, it would also decrease the output frequency. So how do we generate a high output frequency and keep a lower loop gain (N)?
Figure 2: For a standard PLL in this example, the noise from the feedback divider (20 log10(N)) has a 34 dB higher in-band noise compared to the lower yellow plot where N = 1. Image source: Bonnie Baker
With the translation loop architecture, the phase noise of the Offset LO is very important to achieve the best performance at the RF output
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The solution to this issue is to replace the N-divider with a down- converting mixing stage (Figure 3). In Figure 3, the mixer replaces the feedback N divider, resulting in a loop gain equal to 1 (N=1). This operation will greatly diminish the contribution of the feedback loop to the in-band noise floor. For the in- band noise calculation, the value of N is now equal to 1. Using Equation 2, the in-band noise floor for the modified system is as follows: In-band noise floor = FOM PLL + 10 log 10 (F PFD ) + 20 log 10 (N) = -234 dBc/Hz + 10 log 10 (160e6 Hz) + 20 log 10 (1) = -152 dBc/Hz The new in-band noise shows an improvement of 34 dBc/Hz. In Figure 3, the mixer depends on an extremely low noise LO, called Offset LO. F LO ± F RF must equal F PFD to achieve lock. With the translation loop architecture, the phase noise of the Offset LO is very important to achieve the best performance at the RF output. For this reason, engineers would typically design an Offset LO based on voltage- controlled surface acoustic wave (SAW), or oscillators (VCSOs), or comb generators, or dielectric resonator oscillators (DROs). NOTE: For support with designing an Offset LO, contact Analog Devices.
Figure 4: The EV-ADF4401ASD2Z evaluation board for the ADF4401A translation loop module includes an external PFD, a USB interface, and voltage regulators. Image source: Analog Devices
output signal. This is a significant challenge for engineers to address. With traditional designs, engineers usually proceed to multiple design iterations to achieve optimized performance and suitable isolation. Figure 3 shows how the ADF4401A integrates major circuit blocks to provide a fully characterized solution and eliminates the traditionally difficult areas related to the performance and isolation
Translation loop challenges Traditionally, the design of a low- noise translation loop involves the implementation of numerous circuit blocks, resulting in a complex design, usually large, and with limited flexibility. In addition, the entire circuit must be validated and characterized for the target operation. For example, one major
design concern is LO leakage (LO to RF isolation) to the RF
Figure 5: The EVAL-SDP-CS1Z (or SDP-S) controller board is required to provide a USB connection from the EV-ADF4401ASD2Z to a PC for programming. Image source: Analog Devices
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Quickly create low-jitter, high-frequency clocks using a translation loop module
board is not provided in the EV- ADF4401ASD2Z kit. Figure 6 maps out the physical connections of the EV- ADF4401ASD2Z system. The associated Analysis | Control | Evaluation (ACE) Software controls the TL SiP functions. Power is derived from an externally applied 6-volt power supply. The suggested equipment to use with this evaluation board includes a Windows PC, a spectrum analyzer or a signal source analyzer, and three signal generators. The block diagram of the EV- ADF4401ASD2Z shows the ADF4401A module, along with Analog Devices’ HMC3716 PFD, LT6200 op-amp, and the ADG1219 SPDT switch (Figure 7). It is vital to use a PFD that can operate at high frequencies as this minimizes the need for dividers, which can degrade the in-band noise response. The 1.3 GHz phase comparison frequency capability of Analog Devices’ HMC3716 makes it ideal for use in the IF range of the ADF4401A. The ability of such a circuit to compare both frequency and phase eliminates the need for additional circuitry to steer the frequency to the intended output frequency. The HMC3716 becomes the external PFD to complete the offset loop. The high-frequency operation range and ultra-low phase noise floor of the HMC3716 make it possible to design wide- bandwidth loop filters.
Figure 6: An EV-ADF4401ASD2Z setup diagram shows the equipment and connections required to evaluate the ADF4401A, including the SDP-S control board, PC, power supply, signal generators, and spectrum analyzer. Image source: Analog Devices
in translation loop designs. This programmable solution allows engineers to achieve optimized performance on the first effort and reduce time to market. Evaluating the ADF4401A The ADF4401A is designed to help engineers reduce the time to market of high-performance instrumentation, using a frequency generation solution with an RF bandwidth of 62.5 MHz to 8 GHz. By using a down-converting mixer, the ADF4401A has very low in- band noise with a wideband jitter of ~9 femtoseconds (fs) integrated from 100 Hz to 100 MHz. The design and layout techniques inside the ADF4401A enable a typical spurious-free dynamic range of 90 dBc. A package size of 18 x 18 x 2.018 millimeters (mm) substantially reduces board space
compared to a traditional discrete design. To evaluate the device’s performance, designers can use the EV-ADF4401ASD2Z evaluation board (Figure 4). The board includes a complete translation loop, including an external PFD (HMC3716), an active filter (LT6200), and a multiplexer (ADG1609). The EV-ADF4401ASD2Z includes the ADF4401A TL SiP with integrated VCO, a loop filter (5 MHz), a PFD, a USB interface, and voltage regulators. Additionally, the EV-ADF4401ASD2Z requires the EVAL-SDP-CS1Z (SDP-S) system demonstration platform (SDP) (serial) controller board (Figure 5). The board provides a USB connection from a PC to the EV-ADF4401ASD2Z so it can be programmed. The controller
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Figure 7: The EV-ADF4401ASD2Z evaluation board block diagram shows the key components supporting the AD4401A translation loop. Image source: Analog Devices
phase noise floor of the fixture is approximately -160 dBc/Hz. These together give an rms jitter of 12.53 fs in total.
Conclusion
High-speed instrumentation systems require extremely low-jitter clocks to ensure that the output data remains uncompromised. The challenge for engineers is to find suitable devices that can build the high-speed gigahertz clock system. The ADF4401A translation loop greatly simplifies device selection to build the clock system, providing a compact module that ensures low jitter at higher frequencies, while also reducing board space, cost, and time to market.
In Figure 7, the LT6200 op-amp with an LPF configuration attenuates high-frequency spurs, while the ADG1219 switch completes the system’s translation loop. The EV-ADF4401ASD2Z evaluation fixture creates in-band noise plots and jitter measurements as shown in Figure 8.
input is an SMA100B RF and microwave signal generator. The evaluation board’s LO2 in-band noise is approximately -135 dBc/ Hz which is apparent at low offsets up to 300 kHz. The LO2, ADF4401A module, HMC3716 PFD, and loop filter contribute to an in-band noise of about -140 dBc/Hz. The internal phase noise appears between 5 MHz and 50 MHz, and the
In Figure 8, the LO2 and HMC3716
Figure 8: Single sideband phase noise at 5 GHz output, with an external HMC3716 reference of 500 MHz and external LO at 4.5 GHz. Image source: Analog Devices
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How to implement SWaP-C satcom antenna arrays using SMD power dividers and directional couplers Written by Steven Keeping
The space around the Earth is filling fast, and thousands more new satellites are due for launch in the next decade. That’s putting pressure on satellite communications (satcoms) designers from two sides. First, available bandwidth for satcoms in the traditional L, C and X bands is fast being used up. Secondly, commercial satellite builders want their products to be lighter and cheaper to launch. Satcom designers are responding to the lack of RF bandwidth by moving communications from the traditional satellite bands to higher frequency RF bands such as Ku (12 to 18 gigahertz (GHz)). The Ku band offers the potential for greater throughput and is much less congested. With respect to the demand for minimal size, weight,
satellite, such as the antenna array, using advanced packaged surface mount devices (SMDs). This article outlines the benefits of SMD power dividers and directional couplers, key passive elements used in Ku band satcom antenna arrays. The article introduces example devices from Knowles Dielectric Labs, describes how these components meet today’s low-SWaP demands, and how designers can use key performance characteristics of these vital components to optimize antenna array performance.
which essentially perform as mini antenna. The benefits of antenna arrays compared to a conventional antenna for satcoms applications include: ■ Higher gain ■ Increased signal-to-noise ratio (SNR) ■ Steerable transmission beams and enhanced sensitivity to incoming signals from a particular direction ■ Better diversity reception (helps overcome signal fading) ■ Smaller side lobes in the antenna radiation pattern The conventional array structure comprises a 3D-brick configuration made up of electronic assemblies placed side-by-side and attached using multiple connectors and cables. This increases the bulk and complexity of an antenna array, compared with single-antenna dishes.
Advances in antenna arrays
Recent developments in satellite and ground station antennas have seen a move away from single-antenna dishes to antenna arrays. Antenna arrays combine two or more elements, each of
power, and cost (“SWaP-C”), designers are responding by building key elements of the
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How to implement SWaP-C satcom antenna arrays using SMD power dividers and directional couplers
The solution to this bulk and complexity has come from a focus on low SWaP-C that eliminates the brick-like structure resulting from chip-and- wire or hybrid fabrication techniques. Newer designs are made up of multiple
leg of the divider measures one quarter the wavelength of the incoming RF signal. For example, for an incoming signal with a center frequency of 15 GHz, each leg would be 5 millimeters (mm) in length. The legs operate as quarter-wavelength impedance transformers. An isolating resistor is used to match the output ports; because there is zero potential between the output ports, no current flows through the resistor so it doesn’t contribute to resistive losses. The resistor also provides excellent isolation, even when the device is used in reverse (as a power combiner), thereby limiting crosstalk between individual channels. To limit losses as the power is being split, the two output ports of the power divider must each appear as an impedance of 2 Zo. (The 2 Zo in parallel will present an overall impedance of Zo.) For an equal power distribution with R = 2 Z o , then: Z match = √2 Z˳ = 1.414 Z˳ Where: R = the value of the terminating resistor connected between the Figure 2: The basic Wilkinson power divider uses two quarter wavelength impedance transformers and an isolating resistor to match the output ports. Ports 2 and 3 each deliver half the Port 1 input power. Image source: Knowles DLI
microstrip 2D planar elements based on a pc board substrate using SMD packaging. This planar configuration removes the need for many connectors and cables, enhancing SWaP while increasing reliability and simplifying manufacturing (Figure 1). SMDs not only considerably reduce the bulk of the antenna array, but they also allow for the use of a single automated assembly line, dramatically reducing the cost of production compared to a conventional chip-and-wire or hybrid approach. SMD assembly also helps accelerate time to market. Such advances have been made possible because of a new generation of SMD components that can perform reliably in space at high operational frequencies. The devices feature innovative dielectrics, tight tolerance, thin- film manufacturing, and novel microstrip line topologies to Figure 1: The use of low SWaP-C SMD components (right) allows for a reduction in the bulk of satcom antenna arrays compared with a conventional 3D brick assembly (left). Image source: Knowles DLI
provide a high performance/ footprint ratio.
Key antenna array components: power divider A critical passive SMD in the antenna array is the power divider. Individual power dividers split an incoming signal into two or more signals to distribute across the antenna elements making up the array. In its simplest form, the power divider splits the input power (minus some circuit losses) evenly across each output leg, but other forms of power dividers enable the input power to be proportionally shared across the output legs. There are several power divider configurations, but for high- frequency applications, power dividers typically take the form of a microstrip line Wilkinson design (Figure 2). In the basic form, each
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two ports
Z o = the characteristic impedance of the overall system Z match = the impedance of the quarter wave transformers in the legs of the power divider A scattering matrix (S matrix) contains the scattering parameters used to describe the electrical performance of an RF linear network such as a Wilkinson power divider. Figure 3 shows the S matrix for the simple form of power divider shown in Figure 2. Key characteristics of the S matrix include the following: ■ S ij = S ji (showing the Wilkinson power divider can also be used as a combiner) ■ The terminals are matched (S 11 , S 22 , S 33 = 0) ■ The output terminals are isolated (S 23 , S 32 = 0) ■ The power is equally split (S 21 = S 31 ) Losses are minimized when the signals at Ports 2 and 3 are in phase and have equal magnitude. An ideal Wilkinson power divider delivers S 21 = S 31 = 20 log 10 (1/√2) = (-)3 decibels (dB) (i.e., half the input power at each output port).
Figure 4: The PDW06401’s power divider frequency response. RL represents terminal matching (S 11 , S 22 , etc.), Iso is the isolation between output ports (S 23 , S 32 ) and IL is the output power (S 21 , S 31 ). Image source: Knowles DLI
The return loss, isolation, amplitude balance, and phase balance characteristics of a power divider are critical to the performance of the antenna array in the following ways: ■ The return loss of the product should be low because greater losses directly compromise maximum transmitted or received beam energy ■ Product isolation should be high because this impacts the isolation between signal paths in the antenna array and enhances its gain ■ The device’s amplitude balance should approach 0 dB as it affects the amplitude performance and Effective Isotropic Radiated Power (EIRP) of the antenna ■ The device’s phase balance should approach 0° difference as this promotes maximum power transfer and ensures intended phase length for all branches across the network. A large phase imbalance will deteriorate
dividers are a good solution for low SWaP-C antenna array applications. Commercial options for the Ku band include Knowles Dielectric Labs’ PDW06401 16 GHz two-way Wilkinson power divider. Knowles dielectric and thin-film manufacturing know-how have allowed it to fabricate a low-loss, yet compact SMD for service with Ku band satcom antenna arrays. The PDW06401 measures 3 x 3 x 0.4 mm and uses low-loss materials that minimize performance variation over a wide temperature range. The package’s characteristic impedance (Z 0 ) matches the 50-ohm (Ω) requirement needed to minimize the voltage standing wave ratio (VWSR), and hence return losses in high-frequency RF systems. The device features zero nominal phase shift, an amplitude balance of ±0.25 dB and a phase balance of ± 5°. Excess insertion losses are 0.5 dB. Figure 4 illustrates the PDW06401 power divider’s frequency response.
Microstrip line Wilkinson power
Figure 3: Scattering matrix (S matrix) for the Wilkinson power divider shown in Figure 2. Image source: Steven Keeping
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How to implement SWaP-C satcom antenna arrays using SMD power dividers and directional couplers
Figure 5: The coupled port (P3) of a power divider passes on some fraction of the power delivered to the input port (P1), with the rest passing through the transmitted port (P2). The isolated port (P4) is terminated with an internal or external matched load. Image source: Spinningspark at Wikipedia
performance of the antenna array.
These characteristics include the following: ■ The main line loss should be minimized to enhance antenna array gain. This loss is due to resistive heating of the main line and is separate to the coupling loss. The total main line loss is the combination of resistive heating loss plus coupling loss ■ The coupling loss is the reduction in power due to the energy transferred to the coupled and isolated ports. Assuming a reasonable directivity, the power transferred unintentionally to the isolated port should be negligible compared to that transferred intentionally to the coupled port ■ The return loss should be minimized. This is a measure of the amount of the signal that
EIRP and potentially change the radiation pattern of a beam- forming antenna array
typically delivers a fraction of the energy of the main line and often features a smaller connector to distinguish it from the main line Ports 1 and 2. The coupled port can be used to obtain signal power level and frequency information without interrupting the main power flow in the system. Power entering the transmitted port flows to the isolated port and does not affect the output of the coupled port (Figure 5). The key characteristic of a coupler is the coupling factor.
Key antenna array components: directional coupler The directional coupler is another component that performs an important role in antenna arrays by consistently measuring the transmit and receive power of the array elements. The directional coupler is a passive device which couples a known amount of transmission or receive power through to another port from where it can be measured. The coupling is typically achieved by positioning two conductors close to each other such that the energy passing through one line is coupled to the other. The device has four ports: input, transmitted, coupled and isolated. The main transmission line is situated between Ports 1 and 2. The isolated port is terminated with an internal or external matched load (typically 50 Ω), while the coupled port (3) is used to tap the coupled energy. The coupled port
This is defined as:
C 3,1 = 10 log (P 3 /P 1 ) dB The simplest form of coupler
features a right-angled topology whereby the coupled lines run adjacent for one quarter of the wavelength of the input signal (e.g., 5 mm for a 15 GHz signal). This type of coupler typically produces half the input power at Port 3 (i.e., it has a coupling factor of 3 dB), with the power at the transmitted port also reduced by 3 dB. (Figure 6). As is the case with the power divider, there are some key characteristics of the directional coupler that impact the
Figure 6: The simplest form of directional coupler features coupling lines running adjacent for a quarter wavelength of the input signal frequency. Image source: Spinningspark at Wikipedia
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Figure 7: Shown is the frequency response of the FPC06078 directional coupler. The device exhibits a nominal coupling factor of -20 dB and a low insertion loss of 0.3 dB. Image source: Knowles DLI
range of 12 to 18 GHz. The FPC06078 directional coupler features an insertion loss of 0.3 dB and a minimum return loss of 15 dB. The device’s directivity is 14 dB (Figure 8). Conclusion Designers are responding to the demand for low SWaP-C in satcom applications by employing compact SMD passive components. Examples include the power dividers and directional couplers used in the fabrication of the satellite’s antenna arrays. By selecting good quality compact SMD passive devices – that promise superior performance through microstrip line construction and ceramic materials with high dielectric capabilities – designers can take advantage of higher frequency RF bands for satcom applications. Moreover, this new generation of SMD power dividers and directional couplers enables designers to come up with smaller and lighter antenna arrays, while simultaneously enhancing the antennas’ gain and beam forming capabilities.
is returned or reflected by the directional coupler ■ The insertion loss should also be minimized. This is the ratio of a signal level in a test configuration without the directional coupler present, compared to that when the component is present ■ Isolation should be maximized. This is the power level difference between the input port and the isolated port ■ The directivity should be maximized. This is the power level difference between Port 3 and Port 4 of the directional coupler and is related to isolation. It is a measure of the independence of the coupled and isolated ports
While RF directional couplers can be implemented using a variety of techniques, it is the microstrip line type that are finding favor in low SWaP-C satcom applications because of their small size. One example is Knowles’ FPC06078 directional coupler. The device is an SMD microstrip line device that measures 2.5 x 2.0 x 0.4 mm. It has an operating temperature range of -55°C to +125°C and a characteristic impedance of 50 Ω. While the coupling factor is frequency dependent, a high-quality directional coupler will exhibit a relatively flat coupling frequency response. From Figure 7 above, it can be seen that the Knowles device exhibits a nominal
coupling factor of 20 dB, which varies by only 2 dB across an operational
Figure 8: Shown is a graph of the FPC06078 directional coupler’s directivity. For higher antenna array performance, the directivity, which is related to isolation, should be maximized. Image source: Knowles DLI
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Use an agile RF transceiver in an adaptive SDR communication system for aerospace and defense
Written by Stephen Evanczuk
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Figure 1: Traditional superheterodyne radio architectures can meet performance targets, but their complexity prevents them from meeting emerging targets for minimal SWaP. Image source: Analog Devices
Aerospace and defense (ADEF) system designers face unrelenting demand for lower power and more compact communications systems that are capable of an agile response to a dynamic signals environment. Moving beyond traditional radio architectures, software-defined radio (SDR) technology can help meet the fast- changing requirements for ADEF radios, but SDR implementation has presented multiple challenges for meeting both the functional requirements and the need for reduced size, weight, and power (SWaP). This article describes a more effective SDR solution from Analog Devices that can simplify the design of low-power, compact, and agile communications systems without compromising performance. Emerging challenges drive more demanding requirements Designers face a demand for more effective communications in a growing number of industrial and mission-critical applications, including secure
radio communications, adaptive radar, electronic warfare, and enhanced GPS navigation. These new challenges drive a need for enhanced wideband operation, higher dynamic range, greater frequency agility, and reconfigurability. However, these more demanding functional requirements can conflict with the need for lower SWaP as communications systems move to smaller battery-powered platforms, including unmanned aerial vehicles (UAS) and portable units. Design solutions based on traditional discrete superheterodyne radio architectures offer high performance, wide dynamic range, and minimal spurious noise. For designers, the challenge of isolating the desired signal from the intermediate frequency (IF) at the heart of this approach typically results in complex designs with high SWaP and little to no reconfigurability (Figure 1). In contrast, direct conversion (zero- IF) architectures reduce both the filtering requirements and the need for very high-bandwidth analog-to- digital converters (ADCs), resulting in a simpler design that can be
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Use an agile RF transceiver in an adaptive SDR communication system for aerospace and defense
locked loop (PLL) paths: one for the high-frequency RF path and another for the digital clocks and converter sampling clocks. Finally, the device’s digital signal processing block includes an Arm M4 embedded processor that handles self-calibration and control functions (Figure 3). Able to operate in either zero-IF mode or low-IF mode for phase- noise-sensitive applications, the ADRV9002 features transmitter and receiver subsystems offering complete signal chains. Each transmitter subsystem provides a pair of digital-to-analog converters (DAC), filters, and mixers that recombine I and Q signals and modulates them onto the carrier frequency for transmission. Each receiver subsystem integrates a resistive input network for gain control that feeds a current mode passive mixer. In turn, a transimpedance amplifier converts the mixer’s current output to a voltage level that is digitized by an ADC with a high dynamic range. During available transmitter slots in TDD operation or in FDD applications where only one receiver system is used, unused receiver inputs can be used to monitor transmitter channels for LO leakage and QEC, or unused receiver inputs can be used to monitor power amplifier (PA) output signal levels. The latter capability comes into play in the ADRV9002’s integrated
Figure 2: Zero-IF radio architectures can meet the need for higher performance and lower SWaP, but signal isolation is challenging . Image source: Analog Devices
implemented on a single chip (Figure 2). Despite its apparent advantages, the direct conversion architecture presents its own implementation challenges that have limited its widespread adoption. In this architecture, the signal is converted to a radio frequency (RF) carrier at the local oscillator (LO) frequency, but direct current (DC) offset errors and LO leakage can result in errors being propagated through the signal chain. Furthermore, differences in signal paths, even within the same chip, can introduce a gain or phase mismatch of the in- phase (I) and quadrature (Q) signal, resulting in a quadrature error that can compromise signal isolation. SDR technology offers the potential to overcome the limitations of traditional radio architectures, but few solutions can address the broader requirements associated with ADEF applications. Using the Analog Devices’ ADRV9002 RF transceiver, developers can easily meet the need for greater
performance and functionality with the lower SWaP demanded in these applications.
Integrated functionality delivers optimized performance with reduced SWaP Supporting a frequency range from 30 megahertz (MHz) to 6,000 MHz, the ADRV9002 is a highly-integrated transceiver that contains all the RF, mixed signal, and digital functionality required to support a broad array of application requirements. Capable of both time division duplex (TDD) and frequency division duplex (FDD) operation, the device features separate dual-channel direct conversion receiver and transmitter subsystems that include programmable digital filters, DC offset correction, and quadrature error correction (QEC).
Within its on-chip synthesizer subsystem, the ADRV9002 features two distinct phase-
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second pair can substitute when power consumption is critical. For applications characterized by periodic stretches of inactivity, the ADRV9002’s RX monitor mode can be employed. In this mode, the ADRV9002 alternates between a minimal power sleep state and a detect state at a programmed duty cycle. In the detect state, the device activates a receiver and attempts to acquire a signal over a bandwidth and RX LO frequency programmed by the developer. If the device measures signal power level above the programmed threshold, the device exits monitor mode, and the ADRV9002’s blocks are powered up to handle the desired signal. Rapid prototyping and development To help engineers move quickly into evaluation, prototyping, and development, Analog Devices provides extensive hardware and software support of ADRV9002- based systems. ■ For hardware support, Analog Devices offers a pair of ADRV9002-based cards: ■ ADRV9002NP/W1/PCBZ for low band applications operating in the 30 MHz to 3 gigahertz (GHz) range ■ ADRV9002NP/W2/PCBZ for high band applications in the 3 to 6 GHz range Equipped with FMC connectors, these cards support the onboard ADRV9002 with power regulation
Figure 3: The ADRV9002 RF transceiver integrates dual receive (RX) and transmit (TX) subsystems. Image source: Analog Devices
digital pre-distortion (DPD) feature, which uses its monitored PA signal levels to apply the appropriate pre- distortion required to linearize the output. This capability enables the ADRV9002 to drive the PA closer to saturation, optimizing its efficiency.
designed specifically to help developers find a suitable balance between performance and power. At the block level, developers can deploy power scaling on individual signal path blocks to trade reduced performance for lower power consumption. In addition, the blocks in TDD receive (RX) and transmit (TX) frames can be disabled to sacrifice RX/TX or TX/ RX turnaround times for lower power consumption. To further aid the developers’ ability to optimize power versus performance, each ADRV9002 receiver subsystems include two pairs of ADCs. One pair comprises high-performance sigma-delta ADCs, while the
Tuning power and performance
The ADRV9002 device provides a fully integrated solution in a 196- ball chip scale package (CSP) ball grid array (BGA), as well as minimizing size and weight for SDR ADEF communications systems. To help developers further optimize power consumption, the ADRV9002 integrates multiple features
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Use an agile RF transceiver in an adaptive SDR communication system for aerospace and defense
development support through documentation and downloadable software packages. Developers using the development hardware mentioned above can proceed with prototyping and development based on Analog Devices’ product line software or open-source software packages. This article limits the following discussion to product line software. For more information about the open-source development methodology, see Analog Devices’ ADRV9001/2 Prototyping Platform User Guide. Analog Devices stipulates that the term “ADRV9001” in the company’s support documentation is meant as a family designator encompassing the ADRV9002 and other members of the ADRV9001 family. Consequently, references to ADRV9001 in the text or figures below apply to the ADRV9002 device that is the focus of this article.
Figure 4: The highly integrated ADRV9002 transceiver enables developers to quickly implement specialized designs. Image source: Analog Devices
and hardware interfaces, as well as clock and multichip synchronization (MCS) distribution. The cards connect through their FMC connector to an FPGA motherboard, such as AMD’s ZCU102 evaluation board for power and application control. Analog Devices provides a complete schematic and bill of materials (BOM) for its ADRV9002NP radio cards in its support package. The schematic and BOM provide an effective starting point for custom hardware development for most applications. Some applications require an additional RF front-end to meet specific signal conditioning requirements. For these applications, developers only need a few additional components to complete their design (Figure 4). In this example, developers can quickly implement a suitable RF front-end using the following power management components from
Analog Devices: ■ ADRF5160 RF switch ■ HMC8411 low noise amplifier (LNA) ■ ADMV8526 digitally tunable bandpass filter ■ HMC1119 RF digital step attenuator (DSA) ■ HMC8413 driver amplifier ■ HMC8205B PA
Analog Devices provides comprehensive software
Figure 5: The TES tool in the SDK package lets developers quickly begin evaluating the ADRV9002 transceiver on the supported evaluation platform. Image source: Analog Devices
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