F RF
F
PFD
PFD
Figure 1: The standard PLL locks to a lower frequency (F PFD ) reference and generates an output frequency (F RF ). Image source: Bonnie Baker
VCO
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Designers of instrumentation and measurement systems require low- jitter, spurious-free signals in order to provide the signal-to-noise ratios (SNRs) or error vector magnitudes (EVMs) required to meet increasingly demanding customer requirements. At the same time, they are also facing significant pressure to reduce board footprint as well as design cost, and complexity. The latter is critical in to shortening development time to meet narrowing time-to-market windows. To address the many application challenges, engineers need to transition their instrumentation and measurement clocking solutions from custom-made traditionally discrete designs to more integrated solutions. An important step toward this is to use an integrated translational phase-locked loop (PLL). This allows the frequency up- conversion of a traditional voltage- controlled oscillator (VCO) signal, while substantially maintaining the jitter and phase noise of a fixed external local oscillator (LO).
translation loops towards achieving the industry lowest integrated phase noise. By way of example, it introduces the ADF4401A translation loop system-in-package (TL SiP) from Analog Devices and shows how it addresses performance requirements through an output signal with sub-10 femtosecond (fs) rms wideband integrated jitter capability and enhanced isolation to attenuate spurious components, while also meeting designers’ integration, cost, complexity, and time-to- market needs. Traditional PLL vs. translation loop operations The primary purpose of a translation loop is to generate an output signal locked to an input reference signal with significantly reduced in-band phase noise compared to traditional PLLs. A standard PLL consists of a feedback system containing a phase-frequency detector (PFD), charge pump, low-pass filter (LPF), VCO, and a feedback frequency
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